The present invention relates to the design of integrated circuit chips, and more particuarly, to a method and a system for improving the accuracy of existing noise analysis tools in order to identify wires susceptible to noise problems such that other tools can resolve the noise problems in the design.
The continuous scaling of CMOS processes has lead to an increase of noise in digital integrated circuits (ICs). Noise glitches that propagate to a dynamic node or storage element (e.g., a latch) can alter the state of the circuit. This type of noise is often called functional noise. There are two types of noise glitches in a victim net. The first one is coupling noise, which refers to the noise due to the switching of the neighboring nets (referred hereinafter as aggressor nets) that are coupled to the victim net via coupling capacitances or coupling inductances. The second one is referred to propagation noise, which comes from an existing glitch at the input of the victim driver.
To gain a better understanding of the problem addressed by the invention, reference is made to FIG. 1 that graphically illustrates the coupling noise and the propagation noise. The two sources of functional noise are shown occurring in victim net 102. The first one is the aforementioned propagation noise, which is induced by an existing glitch at the input of the victim driver. The second, is the previously mentioned coupling noise, also known as crosstalk noise, which is caused by the simultaneous switching of aggressor net(s) 103 capacitively or inductively coupled to the victim net 102. When the aggressor net 103 is not switching, only propagation noise is seen at the victim net 102. When the arrivals of the aggressor switching signal 110 and the victim input noise pulse 114 are aligned with each other, the combined propagation and coupling noise, e.g., 106, 107, 108, will show in victim net 102. Because of the non-linearity of the victim driver 100, the combined propagation and coupling noise is typically much higher than a superposition of each individual noise. Therefore the victim driver modeling is of particular importance.
It is usually impractically slow to directly analyze the global signal net shown in FIG. 1 using a non-linear circuit analyzer. In order to determine the worst-case noise peak at the input of each victim receiver (e.g. 104), the same circuit has to be re-analyzed with different alignments of arrival times of the aggressor switching signal 110 and the victim input noise glitch 114, which is formidable.
Non-zero noise at both the input and output of the victim driver often makes the gate display a strong non-linear behavior. Therefore, the victim driver must be carefully modeled to ensure a correct functional noise analysis.
Two general approaches have been proposed for modeling the victim driver and the worst-case noise analysis. In the first approach, the victim driver is linearized while keeping the overall aggressor and victim circuit a linear system. The worst-case peak noise alignment between the victim and aggressors are obtained using superposition, which requires having the entire circuit analyzed only once. However, it is rather challenging to model the non-linear behavior of a gate using a simple linear model. By way of example, an extremely simple linear model can consist of only a load independent noise pulse and a driver quiet holding resistance. Such an approach typically introduces a considerable amount of error. It has been reported that for a 130 nm technology, the simplified flow underestimates the noise peak by as much as 70%. The second approach characterizes the driver using a simplified non-linear behavioral model. It consists of a non-linear voltage dependent DC current source and parasitic capacitors. To analyze such a model, a fast non-linear transient analysis engine with numerical integration techniques is employed. One limitation of such a behavioral model is that it works well only for single stage gates. Moreover, the introduction of the non-linear model in the circuit makes the worst-case peak alignment between the victim and aggressors costly. The alignment must be achieved iteratively, and in each iteration, a non-linear analysis of the behavioral model along with the entire interconnect circuit needs to be performed.
Another method that has been reported falls into the first category of computing a linear Thevenin model for the victim driver. To improve the accuracy, the computation of the linear victim driver parameters involves matching the linear driver current to the non-linear current through the interconnect driven by the non-linear behavioral model which, by nature, limits this approach to single-stage driving gates. Additionally, in this model, several Thevenin model parameters, such as the Thevenin resistance and Thevenin voltage pulse width are empirically chosen. However, this approach raises concerns in the computational cost of the model parameters.
Therefore, there is a need in industry for a better approach for determining a linear victim driver model whose model parameters are easy to compute, which is convenient for worst-case noise alignment and which is fully integratable with existing industry standard cell libraries.